8051 IO Mapped interface details

Overview

This is the simplest method of attaching the cs8900 to a cpu.  No GAL is used in this design.  The GAL pins are cross connected as shown below.  This cross connection allows all 6 control inputs and the reset pin to be driven directly from a single CPU register.  Some of the pin on the 26 pin connector are redefined, all are directly driven from 2 CPU registers.

The CPU used for this interface is an cygnal C8051F005 CPU.  In the photo above it is shown interfaced to the development kit for this CPU.  In addition to the ethernet interface components a LM1117-3.3 linear 3.3V regulator was added to supply the current required by the interface.  A MAX3232 3.3V capable RS232 driver was also added to the development kit.

These development kits are available from Digikey as part 336-1017-ND.  Digikey give much more economic shipping options than Cygnal. 

Software support

In the c8051 directory of the code distribution (from here) is an example of the code needed to interface the cygnal cpu mentioned above to the cs8900.  This achieves the best ping results yet at 5ms round trip.

Schematic

The Schematic can be found here.  Modifications to the PCB are described below

Hardware details