Due to the limited number of I/O signals available on an standard 8051 device with external memory a multiplexing mechanism had to be employed to drive the 6 (IOR,IOW, A0-3) control inputs to the CS8900. Using a GAL a combination of serial clocking a direct driving is used to control all 6 control input from 3 CPU outputs. The details can be seen in the GAL equations - serial clocking is used for all but the A0 LSB which is direct driven. Using 3 outputs leaves 2 I/O pins spare on the CPU for an I2C or one-wire interface.
This serial control is very inefficient, it requires many IO operations for a single read or write to the cs8900. However, it works and does allow a variety of small pin count CPUs to be used.
The schematic available here - it differs to the hc11 version in the interface connector and GAL interconnection.
In the dev8051 directory of the code distribution (from here) is an example of the code needed to interface the cygnal cpu mentioned above to the cs8900. This achieves the best ping results yet at 5ms round trip.
Currently only my 8051 development board is supported for simmstick interfacing. People interested in developing interfaces using other CPUs should contact me by email. At some point I would like to support the AT89C4051, but this will require other software since it has very little RAM.